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| MICRONAS INTERMETALL DMA 2275, DMA 2286 C/D/D2-MAC Descrambler MICRONAS Edition May 20, 1992 6251-330-1E DMA 2275, DMA 2286 Contents Page 4 4 4 5 6 6 6 6 6 7 7 7 7 8 8 8 8 8 9 9 10 10 11 12 12 13 13 18 19 19 20 21 23 24 25 26 28 29 29 Section 1. 1.1. 1.2. 2. 3. 3.1. 3.2. 3.3. 3.4. 4. 4.1. 4.2. 4.3. 5. 5.1. 5.2. 5.3. 5.4. 6. 6.1. 7. 7.1. 7.2. 8. 8.1. 8.2. 8.2.1. 8.3. 8.4. 8.4.1. 8.4.2. 8.4.3. 8.4.4. 8.4.5. 8.4.6. 8.4.7. 8.4.8. 8.4.9. 8.5. Title Introduction General Information Environment Chip Architecture Video Processor Code Converter Video Descrambler Interpolation Filter Clamping and Video Gate PRBS Generator Video PRBS Generator Packet PRBS Generator VBI Descrambler Line 625 Processor Majority Decision BCH Check Frame Counter Flywheel RTCI Detector Sound Processor The S Bus Interface and the S Bus Packet Processor Packet Acquisition Packet Descrambler Interface Processor Fast Processor IM Bus Interface IM Bus Addresses and Instructions DRAM Interface DRAM Memory Map Mode Register Pac1 Register Pac2 Register Coeff Register CW Register Error Buffer Packet Buffer Line 625 Buffer Scratch Buffer FP Memory Map 2 DMA 2275, DMA 2286 Contents, continued Page 31 31 31 34 34 35 36 36 37 39 40 42 44 46 Section 9. 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. 9.6.1. 9.6.2. 9.6.3. 9.6.4. 9.6.5. 9.6.6. 10. Title Specifications Outline Dimensions Pin Connections Pin Configuration Pin Descriptions Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Sound DRAM Interface Characteristics Acquisition DRAM Interface Characteristics Waveforms References 3 DMA 2275, DMA 2286 The DMA 2275 and DMA 2286 C/D/D2-MAC Descrambler 1. Introduction 1.1. General Information The DMA 2275 is a digital real-time descrambling processor for the D2-MAC/Packet system. Together with the D2-MAC/Packet decoder chip DMA 2271, it can be used to build up a D2-MAC/Packet conditional access receiver. The DMA 2286 is a digital real-time descrambling processor for the C/D/D2-MAC/Packet system. Together with the C/D/D2-MAC/Packet decoder chip DMA 2281, it can be used to build up a C/D/D2-MAC/Packet conditional access receiver. The programmable VLSI circuits in CMOS technology are housed in 68-pin packages and contain on a single silicon chip the following functions: DMA 2275 and DMA 2286 - descrambling of MAC video signal - interpolation of MAC video signal (aspect ratio 16:9) - descrambling of MAC data packets - descrambling of VBI-teletext - entitlement packet acquisition - supplementary general purpose packet acquisition DRAM DRAM DRAM CASS CCU 3000 NVM 3060 ceivers provide descrambling facility for one video service and up to four audio or data services including VBI-teletext. It is important to notice that the DMA 2275 or DMA 2286 do not include any decryption or security functions. These functions will be carried out by one or more conditional access subsystems (CASS) which communicate with the descrambler chip via the central control unit (CCU) and the IM bus. CASS CCU 3000 NVM 3060 DRAM DRAM D2MAC Baseband Signal VCU 2133 A/D Part DMA 2275 DMA 2271 VCU 2133 D/A Part R G B MCU 2600 TPU 2735 DRAM AMU 2481 S1 S2 S3 S4 Fig. 1-1: Block diagram for a stand-alone D2-MAC decoder - line 625 acquisition - communication with external microprocessor via the IM bus DMA 2286 only - one subframe sound processing C/D/D2-MAC DRAM D/D2MAC Baseband Signal VCU 2133 A/D Part DMA 2286 DMA 2281 VCU 2133 D/A Part R G B MCU 2600 TPU 2740 1.2. Environment AMU 2481 Figures 1-1 and 1-2 show how the descrambler chips DMA 2275 and DMA 2286 can be implemented into a MAC conditional access receiver together with other circuits of ITT's DIGIT 2000 digital TV system. These re- S1 S2 S3 S4 Fig. 1-2: Block diagram for a stand-alone D/D2- MAC decoder 4 DMA 2275, DMA 2286 2. Chip Architecture Figure 2-1 shows the architecture of the descrambling chip DMA 2286. The DMA 2275 architecture is identical to the that of the DMA 2286, except that the sound processor is missing. The chips can be subdivided into several functional blocks. DMA 2275 and DMA 2286: Video Processor - descrambling, panning and interpolation of the video signal PRBS Generator - delivers cut points and cipher streams Sound Processor Line 625 Processor - acquisition of service identification data and real time control information - spectrum descrambling of data burst, packet deinterleaving (one subframe only), sound packet processing (one subframe only) Packet Processor - acquisition of entitlement packets, acquisition of general purpose packets, selection of cipher stream, descrambling of data packets Interface Processor - management of internal and external data transfer Timing Generator - delivers internal chip timing DMA 2286 only: 8 Baseband 8 Video Processor Clamping + Video Gate 8 Baseband Code Converter 8 Video Descrambler 8 Interpolation Filter 8 Video PRBS Generator PRBS Generator Packet PRBS Generator VBI Data Interface Processor Timing Generator Fast Processor Packet Processor Corrected Packet Data Descrambl. Packet Data Packet Acquisition Packet Descrambler Vdd Vdd GND GND Packet Data Burst Data DRAM Interface 8 Addr. R/W Data RAS CAS IM Bus Interface 3 IM Bus Timing Generator Line 625 Acquisition Spectr. Descr. Deinterleaver Sound Processing 12 2 Line 625 Proc. Busy Reset Burst Sync M Sound Proc. DRAM S Bus Fig. 2-1: Block diagram of the DMA 2286 Audio Clock 5 DMA 2275, DMA 2286 3. Video Processor The video processor consists of: - Code Converter - Video Descrambler - Interpolation Filter - Clamping and Video Gate 3.1. Code Converter Input for the video processor is the digitized baseband signal which may be delivered by the VCU 2133 in parallel Gray code or by the UVC 3130 in simple binary code. Therefore, a code converter from Gray to binary code is intended. This converter can be disabled under software control (bit 6 of video mode register) and can be switched from 7 to 8 bit input (test bit TT6). 3.2. Video Descrambler To make the transmitted video signal unintelligible, the luma and/or chroma component are cut into two segments in the MAC encoder. These two segments are then transposed. Task of the video descrambler is to retranspose the segments into their original waveform. Three different video waveforms are possible: - clear - double-cut component rotation - single-cut line rotation The video descrambler has to cope with all these video waveforms. In any case the output signal has a constant delay of 1296 + 4 clock periods in order to avoid synchronization problems during change of the video scrambling mode. For any video configurations not corresponding to Fig. 3, part 2, p. 75 of ref. 1, the video descrambler should be disabled by the software. The signal is then passed through the descrambler unaffected except for the delay of one line. The baseband data burst signal passes the video descrambler through a special shift register, luma and chroma rotation is done in within two video RAMs. The video RAMs are subdivided into chroma and luma segments which are organized as ringbuffer. The concerning address counter is loaded every line with a start value depending on the cut point (CPL or CPC) in case of scrambling, on the pan vector (PANV) in case of 16:9 aspect ratio and in any case on an offset value which is programmable (FP register 33 and 34). The calculation of the start address is done by the Fast Processor in real time. The expansion of the compatible 4:3 part in case of 16:9 aspect ratio is done by reading every third sample twice. 6 3.4. Clamping and Video Gate The DC level of the analog baseband signal is controlled by the clamping circuit of the DMA 2271 or DMA 2281 decoder chip which measures the clamping period of each line. The line store in the video descrambler of the DMA 2275 or DMA 2286 would cause a line delay within the clamping control loop with all corresponding problems. Therefore, the line store of the descrambler chip is bypassed during the clamping period to avoid the line delay. The position of the clamping bypass within the line can be programmed in steps of 99 clock cycles (bit 3-0 in mac_mode register). Clamp position `0' would be located after the first subframe of a D-MAC signal. Clamp position `1' is the default specified in ref 1. The clamp bypass is automatically disabled in line 625 and line 1. Finally, a video gate is provided to switch the luminance component to black and the chrominance component to zero in case of denied access to the video service. This gate can be used in country by country control (CbCC) applications to black out special programs under software control (bit 5 of video_mode register). 3.3. Interpolation Filter If the compatible 4:3 part of a 16:9 picture is to be processed (see Fig. 7, part 2, p. 79 of ref. 1), only this part of the luma and chroma component is read out of the video memory (262 chroma samples, 523 luma samples). An interpolation filter is then used to regain the number of samples expected by the DMA 2271 or DMA 2281 (349 chroma samples, 697 luma samples). The sampling rate ratio is 4:3. The filter function is defined by a set of 16 coefficients, which are programmable. Download of these coefficients into the interpolation filter is a one shot function triggered by software (bit 4 of video_mode register). The interpolation is not influenced by the video scrambling method, because the output signal of the video memory appears unscrambled. The position of the compatible 4:3 part is programmable so that user panning is possible. The panning can also be controlled by the broadcaster when sending real time pan vectors in line 625. The selection of these two panning modes is done by bit 7 of the scram_mode registers. The high frequency losses in the interpolation filter can be partly compensated with a peaking filter. Low peaking increases the signal level about 6 dB at 5 MHz, high peaking increases the signal level about 10 dB at 5 MHz. Peaking is controlled with bit 0 and 1 in the video_mode register. Alternatively the interpolation and peaking filter can be used for baseband filtering. It is then enabled not only during active video, but also during the data burst and VBI transmission. The filter coefficients have to be changed for this application. DMA 2275, DMA 2286 4. PRBS Generator The PRBS generator delivers pseudo random binary sequences to descramble the video signal, packet data, and VBI data. It consists of: - Video PRBS Generator - Packet PRBS Generator 4.1. Video PRBS Generator The Video PRBS generator delivers the cut points for the luma and chroma component as two bytes per line (CPL and CPC). These two bytes are calculated in the PRBS 2 generator described in detail in Fig. 4, part 6, p. 205 and Fig. 3, appendix to part 6, p. 309 of ref. 1. The PRBS 2 generator is clocked 16 times at the beginning of each line in a way that the cut points are available before start of the vision signal. The PRBS 2 generator is loaded with a 60 bit video initialization word (VIW) at the beginning of each frame. The video initialization word is a combination of the 8 bit frame counter (FCNT) and a 60 bit video control word (VCW) which is either one of the local control words (LCW_even and LCW_odd) or one of the video control words received from the CASS (VCW_even and VCW_odd). The selection of even or odd control words is done with the LSB of the conditional access frame counter (CAFCNT). CAFCNT and FCNT are delivered by the line 625 processor. All control words (including the local control words) are read out of the control word registers of the external acquisition DRAM. These registers must be defined by CCU software, which gets control words from the CASS and initializes the local control words with all bits set to `1'. 4.2. Packet PRBS Generator The packet PRBS generator delivers the descrambling sequence for four different data channels which may carry sound or teletext or any other data service. The sequence is used to descramble the 720 useful data bits (after packet header and PT-byte) of packets carrying a scrambled service component. The packet PRBS generator consists of four PRBS 1 generators and four PRBS 3 generators described in detail in Fig. 3, part 6, p. 203, Fig. 5, part 6, p. 207, Fig. 2, appendix to part 6, p. 308 and Fig. 4, appendix to part 6, p. 310 of ref. 1. The four data initialization words (DIW) for the PRBS 1 generators are derived in the same way as in the video PRBS generator and are loaded at the beginning of each frame. Each PRBS 1 generator is then clocked 61 times before receiving the next data packet and the serial output, called packet initialization word (PIW), is loaded into the PRBS 3 generator. The actual descrambling sequence is generated in one of the PRBS 3 generators which is selected by the packet recognition each time a scrambled packet arrives. Channel 1 of the packet recognition selects the PRBS 3 generator which is loaded from the PRBS 1 generator initialized with DCW1 and so on. 4.3. VBI Descrambler Although there is no specification of VBI descrambling in ref. 1, the DMA 2275 or DMA 2286 provide means of descrambling VBI data in a simple manner. The PRBS 1 generator for channel 4 can be used to descramble 2-4 PSK demodulated or duobinary decoded data in the VBI (e.g. VBI-teletext). In this case the PRBS 1 generator will be clocked with 10.125 MHz (D2-MAC) or 20.25 MHz (C/D-MAC) and its serial output is directly used to descramble the VBI data burst. The VBI_PRBS starts with bit 117 and stops after bit 648 (D2-MAC) or bit 1296 (D-MAC) of each data burst of the VBI. The VBI is defined from line 1 to 22 and line 311 to 334 inclusive. Due to the fast processor software (see Fig. 8-1), the PRBS 1 generator can only be loaded in line 7. This means that the VBI descrambler operates from line 1 to line 6 with the data initialization word (DIW) of the previous frame. During line 7 the VBI data output (pin 20) is unpredictable. The delay between data burst input (pin 19) and descrambled VBI data output (pin 20) is 4 clock periods. 7 DMA 2275, DMA 2286 5. Line 625 Processor The line 625 processor is loaded via the data burst input. Line 625 is identified by checking the sync pulse of the data burst input. The normal sync pulse covers only 6 bits of the line synchronization word (LSW), the sync pulse of line 625 covers 102 bits of the frame synchronization data (FSD) and is directly followed by: - 5 bit - 71 bit - 470 bit 546 bit UDT SDF RDF unified data time static data frame repeated data frame line 625 data 5.3. Frame Counter Flywheel The 8 bit frame counter (FCNT) is used in conjunction with the PRBS generators of the descrambling system. The correct acquisition of FCNT is essential to maintain a scrambled service. Therefore, a flywheel technique is used in a way that a free running frame counter is synchronized from time to time with the received FCNT in line 625. In this case even the loss of several line 625 data will not disturb the service acquisition. The CAFCNT LSB is used to select even and odd control words and allows frame accurate switching from one phase to the other. Therefore, a similar flywheel technique is used to protect this LSB. In fact, the internal CAFCNT LSB is the 9th bit of the free running frame counter and is synchronized by the actually transmitted CAFCNT LSB after a majority decision over several frames. 5.4. RTCI Detector A special TDMCID code in the TDMCTL indicates the presence of real time control information (RTCI) transmitted instead of TDMS and LINKS. TDMCID = `81' (hex) is defined to signal the transmission of real time panning information. The pan vector PANV is needed for panning the 4:3 portion of a 16:9 picture. In this case the 63 bits of TDMS and LINKS are substituted with 56 bits of PANV. PANV is organized in seven bytes giving the pan vector for seven consecutive frames starting from the second frame after transmission. Each byte of PANV defines in 2's complement format the offset of the 4:3 portion from the center position (see Fig. 7, part 2, p. 79 of ref. 1). After detection of TDMCID = `81' (hex) the following seven bytes are stored in a FIFO which is read out once a frame with one frame delay. If the FIFO is empty the last byte will be repeated until a new pan vector is received. The TDMCTL transmitting the pan vector will be stored into the line 625 buffer like any other TDMCTL information. If user panning is selected by software, the pan vector inside TDMCID will be ignored and a user defined pan vector will be used instead, allowing the user to pan the picture himself. In any case the recently transmitted pan vector in line 625 is stored in the pan output register to allow the software to make a smooth return between different pan positions. In case of C-MAC or D-MAC the 546 bits of UDT, SDF and RDF are interleaved with PRBS data. The PRBS data are discarded by using a clock divider so that the clock frequency for the line 625 processor is unique for C-, D- and D2-MAC (10.125 MHz). UDT, SDF and the error corrected TDMCTL data are stored into the external acquisition DRAM (see figure "Line 625 Buffer") and are updated every frame. The line 625 processor consists of: - Majority Decision - BCH Check - Frame Counter Flywheel - RTCI Detector 5.1. Majority Decision The RDF consists of five successive identical 94 bit data blocks transmitting time division multiplex control (TDMCTL) information. The fivefold repetition is used by a 3 of 5 majority decision including the BCH suffix. 5.2. BCH Check SDF and TDMCTL are each protected by a 14 bit BCH suffix. The BCH check is only used for error detection. BCH check for the TDMCTL is done after majority decision. The complete SDF (71 bit) or TDMCTL (94 bit) information is stored into DRAM together with two error flags SDF_Error and TDM_Error indicating the result of the BCH check. 8 DMA 2275, DMA 2286 6. Sound Processor The DMA 2286 contains an additional sound processor, which is loaded via the data burst input. The sound processor consists of: - spectrum descrambler - deinterleaver - sound processing - S Bus interface These blocks are identical to the sound processing blocks of the DMA 2281 (see ref. 2). Both sound processors are able to decode 4 sound channels out of one single subframe. The subframe position is programmable to allow full channel data reception. On the DMA 2286 the output of the deinterleaver is internally fed to the packet descrambler and the descrambled packets are going back to the sound processor. The sound processor needs a separate external 64 k x 1 bit DRAM, which is independent from the acquisition DRAM and is not accessible by software. 6.1. The S Bus Interface and the S Bus The S bus has been designed to connect the digital sound output of the DMA 2271 or DMA 2281 MAC Decoder or the MSP 2400 NICAM Demodulator/Decoder to audio-processing ICs such as the AMU 2481 Audio Mixer or the ACP 2371 Audio Processor etc., and to connect these ICs one to the other. The S bus is a unidirectional, digital bus which transmits the sound information in one direction only, so that it is not necessary to solve priority problems on the bus. The S bus consists of the three lines: S-Clock, S-Ident, and S-Data. The DMA 2271, DMA 2281 or the MSP 2400 generates the signals S-Clock and S-Ident, which control the data transfer to and between the various processors which follow the DMA 2271, DMA 2281 or the MSP 2400. For this, the S-Clock and S-Ident inputs of all processors in the system are connected to the S- Clock and S-Ident outputs of the DMA 2271, DMA 2281 or the MSP 2400. S-Data output of the DMA 2271, DMA 2281 or MSP 2400 is connected to the S-Data input of the next following AMU, the AMU's S-Data output is connected to the ACP's S-Data input and so on. The sound information is transmitted in frames of 64 bits, divided into four successive 16-bit samples. Each sample represents one sound channel. The timing of a complete transmission of four samples is shown in Fig. 9-13, the times are specified under "Recommended Operating Conditions". The transmission starts with the LSB of the first sample. The S-Clock signal is used to write the data into the receiver's input register. the S-Ident signal marks the end of one frame of 64 bits and is used as latch pulse for the input register. The repetition rate of S-Ident pulses is identical to the sampling rate of the D/D2-MAC or NICAM sound signal; thus it is possible to transfer four sound channels simultaneously. The S bus interface of the DMA 2286 mainly consists of an output register, 64-bit wide. The timing to write bit by bit is supplied by the Audio-Clock signal. In the case of an S-Ident pulse, the contents of the output register are written to the S-Data output. The S_Bus_Data line of the DMA 2286 can be connected to that of the DMA 2281 if only one audio processor AMU 2481 is available. In this case each S_Bus channel of both DMA chips can be enabled or disabled under software control. 9 DMA 2275, DMA 2286 7. Packet Processor The packet processor is loaded via the scrambled packet data input with packets of one subframe delivered by the DMA 2271 or DMA 2281 and additionally has an internal connection to the deinterleaver of the DMA 2286 for packets of the other subframe. Packet data on these lines are already spectrum descrambled and deinterleaved. The packet header and the PT byte have already been corrected. The transmission of each packet starts with a `0' bit followed by 751 bit packet data with a unique bit rate of 10.125 MHz (for C-, D- and D2-MAC). To avoid simultaneous reception of two packets from different subframes, the packet output of the DMA 2286 has to be delayed in reference to the packet output of the DMA 2281. This can be done with the CD bit in IM_Bus register 197. The packet processor consists of: - Packet Acquisition - Packet Descrambler 7.1. Packet Acquisition Task of the packet acquisition is to select specific packets out of the packet multiplex. In case of C- or D-MAC packets can be located in one or two subframes, therefore, the packet selection will be repeated in the second subframe if necessary. The selected packets can be error corrected if needed and are stored into packet buffers which are located in the acquisition DRAM. Due to timing conflicts with the line 625 acquisition, it is not possible to acquire packets in the last (82nd) packet slot of each subframe. Additionally, all packets of both subframes are available on a separate output pin (corrected packet data output), only that the selected packets are replaced by their error corrected equivalents. The most common application of the packet acquisition will be the selection of the following packets: - `0' packets - EMM packets - ECM packets - BI packets - 2nd level teletext packets - general purpose data packets The `0' packets are forming the service identification (SI) channel. The first thing the receiver software has to do is to monitor the SI channel and to configure the receiver according to the SI information. `0' packets are either hamming protected (H[8,4]) or golay protected (Golay 10 [24,12]). The SI channel is subdivided into 16 data groups which can be identified by the data group (TG) byte immediately following the PT byte of the packet header. The EMM and ECM packets are essentially carrying encryption keys and control words. Their packet addresses are indicated by the LISTX, ACMM and ACCM parameters of the service identification channel. EMM packets can be addressed to a single customer or a group of customers by means of an address extension field of up to 36 bit, immediately following the PT byte. EMM and ECM packets are highly error protected (Golay [24,12] or Hamming [8,4]). BI packets are carrying additional interpretation data related to sound packets with the same packet address. They are selected by their PT byte (`00' or `3F'). BI packets are not error corrected. Second level teletext packets can be selected to do Golay [24,12] correction. They are available then on the corrected packet data output which can be connected to the teletext processor TPU 2740. Every selected packet is CRC checked regardless of packet type and error protection. The CRC check is done over the full range of 720 bit and does not change any packet data. CRC check, Golay [24,12] and Hamming [8,4] error correction is done in real time, i.e. with 10.125 MHz. In case of packets with Golay [24,12] error protection, the protection bits will be removed before storing these packets into the packet buffer. the packet length is therefore reduced from 96 bytes (full length packet) to 48 bytes (half length packets), doubling the possible number of packets in the related packet buffer. The result of CRC check and the number of uncorrectable Golay or Hamming codes per packet is indicated in a special packet error buffer which holds up to 16 error bytes for every packet buffer. In case of full length packets, only every second entry of the error buffer is used. Every selected packet is stored into the external acquisition DRAM of the descrambler chip. The DRAM includes 8 independent packet buffers, each offering the data capacity to store 8 full length packets or 16 half length packets. The packet buffers can be read out by software at any time and in any sequence. There are two ways to use these packet buffers. One is the "standard" buffer application where the buffer is automatically closed when it is filled up with packets. The buffer must then be reopened by software to start packet acquisition again. The second way is the "ring" buffer application where the packet buffer is always open and the oldest packets in the buffer are overwritten by the next incoming packets. Each packet buffer can be monitored by reading its buffer status. The buffer status is located in the FP memory and includes a buffer pointer (bit 4-0) which indicates the position where the next packet will be stored in numbers of half length packets. In ring buffer application this pointer runs modulo 16 and in standard buffer application the pointer stops at 16. DMA 2275, DMA 2286 The buffer application (standard/ring) can be defined with bit 5 in the buffer status register. Bit 7 allows to close or reopen the buffer under software control. Bit 6 defines the buffer increment. that means whether the buffer will store full length (96 byte) packets or half length (48 byte) packets. Each of the 8 packet buffer is attached to a programmable packet filter which selects specific packets out of the packet multiplex depending on packet address (PA), continuity index (CI), packet type (PT) and packet address extension (PAE). The packet address extension can be used to select EMM packets by their specific customer address (UCA, SCA, CCA) or to select ECM packets by command identification (CI or to select the data group type (TG) of `0' packets. This selection is done after error correction. Each of the 8 packet filter is controlled by a set of registers located in the acquisition DRAM and programmable by software. The `packet address base' (PAB) registers define the 10 bit packet address and the continuity index. The `packet address extension' (PAE) registers define up to 36 bit of the address extension field. The `packet selection control' (PSC) registers define how packets will be selected, error corrected and linked together. The software should take care of conflicts like programming different packet filters with the same conditions. There must be at least one difference in the combination of packet address, continuity index, packet type, and packet location. Otherwise the result of the packet selection will be undefined. If packet link is activated, the first packet meeting all programmed conditions is defined as sync packet. Selection of continuation packets is done according to the packet link status. In case of CI link, the continuity index of following packets will be ignored. In case of PT link, the packet type selection is changed to PT2. a special bit in the buffer status indicates if this procedure has been activated by the first sync packet. The packets are then stored into the packet buffer in the same order as they are transmitted. The choice of packet link is independent from the choice of buffer application. Depending on the page select bit in the PSC register the packet address extension is checked in every packet or only in the sync packet. To select linked EMM packets by customer address this bit should be `0', to select linked `0' packets by data group type this bit should be `1'. 7.2. Packet Descrambler Main task of the packet descrambler is to detect those sound or data packets that have to be descrambled. Four different packet addresses can be recognized. After detection of such a packet the concerning PRBS 3 generator is selected and produces an output sequence of 720 bit to descramble the packet data. The PT-Byte of each selected packet is decoded to disable the PRBS 3 generator output in case of BI packets (`00' or `3F'). The packet descrambler can be switched to "automatic" operation. In this mode the 4 center bits of the packet address are ignored by the packet address comparator. In case of C- or D-MAC, packets carrying one digital component can be inserted in one or both subframes, therefore the packet recognition will be repeated in the second subframe if necessary. Because the packet header is not scrambled, the packet recognition has about 20 clock cycles to compare the packet address before start of the descrambling sequence. Therefore there is only a 4 clock cycle delay between packet input and output. Additionally, a packet gate is provided to remove packets form the packet output in case of denied access to that particular service. These packets are not physically removed - only the 720 bits after the packet header are set to `1'. Any other packet not selected by the packet recognition passes through the packet descrambler unaffected but with a delay of 4 clock periods. The packet recognition is controlled by a set of registers located in the acquisition DRAM and programmable by software. The `scrambled packet address' (SPA) registers define the 10 bit packet address and the `scrambled packet status' (SPS) registers define packet location and status. The software should take care of conflicts like programming different SPA and SPS registers in the combination of packet address and packet location. Otherwise, the result of the packet recognition will be undefined. 11 DMA 2275, DMA 2286 8. Interface Processor The interface processor consists of: - Fast Processor - IM Bus Interface - DRAM Interface - control of interpolation filter Fig. 8-1 shows roughly when the different FP tasks are executed within a frame period. In normal operation the FP will not be directly accessed from outside, that means that the CCU software will not see another processor on the descrambling chip but only a set of registers and buffers which are located either in the acquisition DRAM or in the FP internal memory. The CCU can access both memories via IM Bus. Changing any register in the DRAM memory by CCU software will not effect the descrambler hardware immediately. The FP will read or update the DRAM memory only on frame boundaries, i.e. from line 622 to line 7 inclusive. Changing registers in the FP memory by CCU software will effect the descrambler hardware immediately. - support of packet acquisition - support of line 625 acquisition - initialization of PRBS generators - control of video descrambler 8.1. Fast Processor The fast processor (FP) is a RISC-type 12 bit microcontroller built in CMOS technology. The maximum clock frequency of 40 MHz and the internal architecture that allows parallel ALU operation and data transfer to or from internal RAM, make it applicable for very high speed tasks, such as control and parameter calculation in digital signal processors. The FP is embedded in the DMA 2275 or DMA 2286 with 256 x 12 bit RAM and 2K x 20 bit ROM and runs with 20.25 MHz. The FP performs the following tasks: - data transfer to and from DRAM interface - data transfer to and from IM Bus interfaces Line 1 2 3 4 5 6 7 8 line_sync line_sync line_sync line_sync line_sync line_sync line_sync line_sync prbs2 prbs2 prbs2 prbs2 prbs2 prbs2 prbs2 prbs2 manager manager manager manager manager manager manager line_625_store vcw_update dcw1_update dcw3_update cw_conversion psc_update prbs_init prbs2_init enable_imbus packet_sync packet_read packet acquisition pae_comparator buffer_manager imbus packet_link packet_store packet_error 622 623 624 625 line_sync line_sync line_sync line_ sync prbs2 prbs2 prbs2 manager manager manager pae_low_update pae_high_update mode_update line_625_sync coeff_update disable_imbus disable_packet_sync enable_packet_sync pab_update dcw2_update dcw4_update Fig. 8-1: Task manager 12 DMA 2275, DMA 2286 8.2. IM Bus Interface The INTERMETALL Bus (IM Bus for short) was designed to control the DIGIT 2000 ICs by the CCU Central Control Unit. Via this bus the CCU can write data to the ICs or read data from them. This means the CCU acts as a master, whereas all controlled ICs have purely slave status. The IM bus consists of three lines for the signals Ident (ID), Clock (CL) and Data (D). The clock frequency range is 50 Hz to 1 MHz. Ident and clock are unidirectional from the CCU to the slave ICs, Data is bidirectional. Bidirectionality is achieved by using open-drain outputs. The 2.5 ... 1 kOhm pull-up resistor common to all outputs must be connected externally. The timing of a complete IM Bus transaction is shown in Fig. 9-12. In the non-operative state the signals of all three bus lines are High. To start a transaction the CCU sets the ID signal to Low level, indicating an address transmission, and sets the CL signal to Low level, as well as to switch the first bit on the Data line. Then eight address bits are transmitted, beginning with the LSB. Data takeover in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal switches to High, initiating the address comparison in the slave circuits. In the addressed slave, the IM bus interface switches over to Data read or write, because these functions are correlated to the address. Also controlled by the address the CCU now transmits eight or sixteen clock pulses, and accordingly one or two bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. For future software compatibility, the CCU must write a zero into all bits not used at present. Reading undefined or unused bits, the CCU must adopt "don't" care behavior. 8.2.1. IM Bus Addresses and Instructions On the DMA 2275 or DMA 2286 the IM bus registers 5-10 are used to transfer data to and from the acquisition DRAM. This is done by subaddressing. Each data transfer is preceded by the transfer of the extension address highbyte and the read or write address lowbyte. The subsequent data is written to or read from the DRAM according to the preceding address command. The DRAM address is then incremented internally to prepare for the next data transfer (auto address increment). The status register is used to synchronize the data transfer between CCU and the descrambler in terms of handshaking. For this purpose the CCU has to read the busy bit and has to wait until this bit is cleared. Reading the busy bit can be done with a normal IM bus read access which takes 16 IM Bus clock cycles or by checking the IM Bus busy signal at pin 47 which delivers the busy bit as a physical signal. The same IM Bus registers can be used to transfer data to and from the FP internal memory. Loading the write address register (6) with an 8 bit FP address and setting bit 10 at the same time writes the 12 bit content of the extension address register (5) into the FP RAM. Loading the read address register (7) with an 8 bit FP address and setting bit 10 at the same time starts transfer of 12 bit FP data into the data (8) and status (9) register. The 8 LSBs are copied into the data register in normal order and the 4 MSBs are copied into the extension data of the status register but in reversed order. The DMA 2286 carries a second set of IM Bus registers, which are used to control the sound processing. These IM Bus registers are a copy of the registers of the DMA 2281 with identical functions and addresses (194-198, 203-206 and 208-210). The CCU selects the IM Bus registers of the descrambler chip by writing `1' into the chip select register 198. This disables all parallel IM Bus registers of the decoder chip except the chip select register. Writing `0' into the chip select register disables all IM Bus registers of the descrambler chip, except the subaddressing registers 5-10 and the chip select register 198. 13 DMA 2275, DMA 2286 Table 8-1: Data transfer between CCU and DMA 2275/2286 Addr. No. Bit No. Direct. W 0 6 W 0 7 W 0 8 R/W 0 0 0 0 0 0 0 0 0 MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 5 this is an 8 bit register 9 R this is an 8 bit register 0 EXA Extension Address 0 WRA Write Address 0 RDA Read Address 0 DAT Data 0 EXD BUS Busy Extension Data 0 0 TT6 0 TT5 0 TT4 0 TT3 TT2 RRQ 0 TT1 0 WRQ 0 TT0 0 Read Write Request Request 10 W TT15 0 TT14 0 TT13 TT12 0 TT11 0 C1U Mode Update TT10 0 C1E Channel Enable TT9 0 TT8 0 TT7 0 203 W S 194 W S 195 W S 196 W S DRS Data Rate Select 0 C1M Channel Mode HQ H C2M Channel Mode HQ H C3M Channel Mode HQ H C4M Channel Mode HQ H AUM CD Auto Mode Chip Defin. L 0 C2U Mode Update 0 C2E Channel Enable L 0 C3U Mode Update 0 C3E Channel Enable L 0 C4U Mode Update 1 C4E Channel Enable L 0 0 197 W 1 CS 198 W Chip Select 0 1 0 0 0 0 C1A Channel Packet Address 0 C2A Channel Packet Address 0 C3A Channel Packet Address 82 C4A Channel Packet Address 0 SFS Subframe Select 106 0 204 W 0 0 0 0 DSB Disable S Bus 0 P0C P0 Clear 0 P0R P0 Reset 0 0 205 W TT15 0 206 R 0 208 R S 209 R 0 TT14 0 P0S TT13 0 C4S TT12 0 C3S Status 0 TT11 0 C2S 0 TT10 0 C1S 0 0 TT9 0 0 TT8 0 TT7 0 0 DGT Data Group Type 0 TT6 0 TT5 0 0 0 0 0 SBE S Bus Enable 12 TT2 0 TT1 0 0 0 TT4 0 TT3 TT0 0 0 BER Bit Error Rate 0 C4L Coding Law CH4 HQ H S PSH Packet 0 Syndrom High Byte PDH Packet 0 Data High Byte L 0 C3L Coding Law CH3 HQ H 0 C2L Coding Law CH2 HQ H C1L Coding Law CH1 HQ H L S S PSL Packet 0 Syndrom Low Byte PDL Packet 0 Data Low Byte L L 210 R Bit must be set to zero for write registers (W) and are don't care for read registers (R) 14 DMA 2275, DMA 2286 Table 8-2: IM Bus register of DMA 2275/2286 Address 5 6 Label EXA WRA Bit No. 0-11 0-11 Function extension address write address bit 10: test option 2 1 = write (EXA) into fp_ram, address = (WRA) 7 RDA 0-11 read address bit 10: test option 2 1 = read fp_ram into DAT and EXA, address = (RDA) bit 11: test option 1 1 = causes fp_jump to (EXA) 8 9 DAT WRQ RRQ BUS EXD 10 TT0 TT1 TT2 TT3 TT4 TT5 TT6 TT7 TT8 TT9 TT10 TT11 TT12 TT13 TT14 TT15 0-7 0 1 2 3-6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data (from dram or fp_ram) write request read request imbus busy 1 = imbus interface busy extension data 4 msb of fp_data, but in reverse order for test only bypass line memory for test only for test only for test only for test only gray decoder input 0 = 7 bit 1 = 8 bit for test only for test only for test only for test only for test only for test only for test only for test only for test only 15 DMA 2275, DMA 2286 Table 8-3: IM Bus register of the DMA 2286 Address 203 Label C1A C1E C1U C1M Bit No. 0-9 10 11 12-15 Function channel 1 packet address channel 1 packet selection enable channel 1 mode update channel 1 mode linear/nicam hamming/parity protection high/medium quality stereo/mono channel 2 channel 3 channel 4 subframe select SFS = sample number of the first bit in the selected subframe examples: DRS = 1, first subframe SFS = 7 DRS = 1, second subframe SFS = 106 DRS = 0, first subframe SFS = 14 chip definition 0 = DMA 2271/2281 1 = DMA 2286 undelayed packet output of sound proc. packet output delayed by 128 s 194 195 196 197 see register 203 see register 203 see register 203 SFS 0-10 CD 13 AUM 14 auto mode 0 = auto mode off 1 = sound coding in packet header data rate select 0 = 10.125 Mb/s 1 = 20.25 Mb/s D2 MAC C/D MAC DRS 15 198 CS 14, 15 chip select 0 = imbus of DMA 2271/2281 active 1 = imbus of DMA 2286 active s_bus enable, each bit enables one s_bus channel channel 1 enable channel 2 enable channel 3 enable channel 4 enable data group type selection packet 0 reset 1: select first byte in packet 0 buffer (first byte = data group type DGT) packet 0 clear 1: enable packet 0 buffer to store next packet 0 disable s_bus data output (pin 66) 0 = enabled 1 = high impedance 204 SBE 0-3 DGT P0R P0C DSB 4-7 8 9 10 16 DMA 2275, DMA 2286 Table 8-3, continued Address 205 Label T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 206 BER Bit No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0-7 Function for test only for test only for test only for test only for test only for test only enable packet descrambler for test only disable error concealment for test only for test only for test only for test only for test only for test only for test only bit error rate: number of erroneous bits of 82 packet headers within one frame, detected by the golay decoder status of sound signal selected by C1A 0: sound signal is inactive or interrupted 1: sound signal is present status of sound signal selected by C2A 0: sound signal is inactive or interrupted 1: sound signal is present status of sound signal selected by C3A 0: sound signal is inactive or interrupted 1: sound signal is present status of sound signal selected by C4A 0: sound signal is inactive or interrupted 1: sound signal is present status of packet 0 buffer 0: packet 0 selected by DGT not received 1: packet 0 received coding law of sound signal selected by C1A coding law of sound signal selected by C2A coding law of sound signal selected by C3A coding law of sound signal selected by C4A L = 0: companded law 1: linear law H = 0: first level protection 1: second level protection HQ = 0: medium quality sound 1: high quality sound S = 0: monophonic sound 1: stereophonic sound C1S 10 C2S 11 C3S 12 C4S 13 P0S 14 208 C1L C2L C3L C4L 0-3 4-7 8-11 12-15 17 DMA 2275, DMA 2286 Table 8-3, continued Address 209 Label PSL PSH Bit No. 0-7 8-15 Function packet 0 syndrom low byte packet 0 syndrom high byte PSL + PSH = 0: packet 0 received without error PSL + PSH > 0: packet 0 received with error packet 0 data low byte packet 0 data high byte 210 PDL PDH 0-7 8-15 8.3. DRAM Interface The data transfer between descrambler chip and acquisition DRAM interface controlled by the FP. The external 64 k x 1 bit DRAM has to store the following data streams: - line 625 - packet bus - IM bus 28 byte/40ms 5600 bit/s 2 x 96 byte/448 s 3430000 bit/s 500000 bit/s The 1 bit DRAM interface offers a maximum data rate of 5.0625 Mbit/s by using four 20.25 MHz cycles for one page mode read or write access. A 150 ns DRAM fulfills the access time requirements. Fig. 9-14 shows the DRAM interface waveform. Refresh of the DRAM is controlled by the FP, which starts a number of refresh cycles within every line. An 8 bit refresh is performed to allow the use of 256 Kbit DRAMs. The acquisition DRAM is used on one side to store received packet data and line 625 information needed by the CCU and the conditional access subsystem (CASS) and on the other side to store control information needed by the descrambler chip (e.g. control words, filter coefficients, packet addresses etc.). Therefore, the descrambler chip does not include special IM bus registers except those for subaddressing and sound processing (on the DMA 2286 only). The upper end of the DRAM address space can be used as a scratch buffer for the CCU software. This DRAM area is also refreshed and will never be used by the descrambler chip. 18 DMA 2275, DMA 2286 8.4. DRAM Memory Map 8.4.1. Mode Register Name mode_register access_mode Address 0000 0000 Function 6*8 bit 8 bit bit 0: bit 1: bit 2: bit 3: bit 4: bit 5: bit 6: bit 7: 8 bit bit 0: bit 1: bit 2: bit 3: bit 4: bit 5: bit 6: bit 7: 8 bit bit 0: bit 1: bit 2: bit 3: bit 4: bit 5: bit 6: bit 7: video cond. access data1 cond. access data2 cond. access data3 cond. access data4 cond. access not used not used not used peaking select peaking baseband filter interpol. filter load coeff black out gray decoder line delay video descrambling video rotation aspect ratio vbi descrambling coeff clock not used not used user panning clamp position clamp bypass freq select decoder sync mac select (0 = free / 1 = conditional) (0 = free / 1 = conditional) (0 = free / 1 = conditional) (0 = free / 1 = conditional) (0 = free / 1 = conditional) video_mode 0008 (0 = low / 1 = high) (1 = on) (1 = on) (1 = on) (1 = now) (1 = on) (1 = on) (1 = off) (0 = on) (0 = double / 1 = single) (0 = 4:3 / 1 = 16:9) (1 = on) (1 = on) (1 = on) scram_mode 0010 mac_mode 0018 8 bit bit 3-0: bit 4: bit 5: bit 6: bit 7: (1 = on) (0 = 50 Hz / 1 = 60 Hz) (1 = locked) (0 = d2 / 1 = d) (2's complement) (2's complement) pan_vector pan_output 0020 0028 8 bit bit 7-0: user pan vector 8 bit bit 7-0: pan vector output Edition: June 12, 1992 6251-330-1E 19 DMA 2275, DMA 2286 Mode Register bit address 0000H 0008H 0010H 0018H 0020H 0028H 7 6 5 4 3 2 1 0 Access_mode < 7-0 > Video_mode < 7-0 > Scram_mode < 7-0 > Mac_mode < 7-0 > Pan_vector < 7-0 > Pan_output < 7-0 > 8.4.2. Pac1 Register Name pac1_register spa_reg sps_reg Address 0100 0100 0140 Function 12*8 bit 4*2*8 bit bit 9-0: packet address 4*8 bit bit 0: bit 2,1: packet descrambling (1 = on) packet location (01 = 1st subframe) (10 = 2nd subframe) (00 = both subframes) (11 = both subframes) packet remove (1 = on) automode (1 = on) bit 3: bit 4: SPA Register bit address 0100H 0108H 0110H 0118H 0120H 0128H 0130H 0138H SPA4 < 7-0 > SPA4 < 9, 8 > SPA3 < 7-0 > SPA3 < 9, 8 > SPA2 < 7-0 > SPA2 < 9, 8 > SPS Register bit 3 2 1 0 address 0140H SPA1 < 9, 8 > 7 6 5 4 7 6 5 4 3 2 1 0 SPA1 < 7-0 > SPS1 < 4-0 > SPS2 < 4-0 > SPS3 < 4-0 > SPS4 < 4-0 > 0148H 0150H 0158H 20 DMA 2275, DMA 2286 8.4.3. Pac2 Register Name pac2_register pab_reg Address 0160 0160 Function 72*8 bit 8*2*8 bit bit 9-0: packet address bit 10,11: continuity index 8*5*8 bit bit 35-0: packet address extension 8*2*8 bit bit 0: packet acquisition bit 2,1: packet location (1 = 0) (01 = 1st subframe) (10 = 2nd subframe) (00 = both subframes) (11 = both subframes) bit 3: cont. index select (1 = on) bit 6-4: packet type select (000 = ignore packet type) (001 = select F8 or 00) (010 = select C7 or 3F) (110 = select F8) (101 = select C7) (100 = select 00) (111 = select 3F) bit 8,7: packet protection (00 = not protected) (01 = 8 byte Hamming [8,4]) (10 = full Hamming [8,4]) (11 = Golay [24,12]) bit 11-9: packet addr. extens. (000 = ignore pack. extension) (001 = select1lsb of CI) (010 = select 4bit of TG) (011 = select 7msb of CI) (100 = select 8bit of CI) (101 = select 12 bit of CCA) (110 = select 24bit of SCA (111 = select 36bit of UCA) bit 13,12: packet link (00 = no packet link) (01 = link by PT) (10 = link by CI) (11 = not defined) bit 14: pae select (0 = in every packet) (1 = in sync packet only) pae_reg psc_reg 01e0 0320 21 DMA 2275, DMA 2286 PAB Register bit address 0160H 0168H 0170H 0178H 0180H-01d8H 7 6 5 4 3 2 1 0 PAB1 < 7-0 > PAB1 < 11-8 > PAB2 < 7-0 > PAB2 < 11-8 > PAB3 - PAB8 PAE Register bit address 01e0H 01e8H 01f0H 01f8H 0200H 0208H-0228H 0230H-0250H 0258H-0278H 0280H-02a0H 02a8H-02c8H 02d0H-02f0H 02f8H-0318H 7 6 5 4 3 2 1 0 PAE1 < 7-0 > PAE1 < 15-8 > PAE1 < 23-16 > PAE1 < 31-24 > PAE1 < 35-32 > PAE2 < 35-0 > PAE3 < 35-0 > PAE4 < 35-0 > PAE5 < 35-0 > PAE6 < 35-0 > PAE7 < 35-0 > PAE8 < 35-0 > PSC Register bit address 0320H 0328H 0330H 0338H 0340H-0398H 7 6 5 4 3 2 1 0 PSC1 < 7-0 > PSC1 < 14-8 > PSC2 < 7-0 > PSC2 < 14-8 > PSC3 - PSC8 22 DMA 2275, DMA 2286 8.4.4. Coeff Register Name coeff_register a3_coeff a2_coeff a1_coeff a0_coeff b3_coeff b2_coeff b1_coeff b0_coeff c3_coeff c2_coeff c1_coeff c0_coeff d3_coeff d2_coeff d1_coeff d0_coeff Address 0400 0400 0408 0410 0418 0420 0428 0430 0438 0440 0448 0450 0458 0460 0468 0470 0478 Function 16*8 bit bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: bit 5-0: 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value 6 bit integer value (5) (13) (0) (1) (38) (46) (0) (25) (38) (25) (0) (46) (5) (1) (0) (13) Coeff Register bit address 0400H 0408H 0410H 0418H 0420H 0428H 0430H 0438H 0440H 0448H 0450H 0458H 0460H 0468H 0470H 0478H 7 6 5 4 3 2 1 0 A3_coeff < 5-0 > A2_coeff < 5-0 > A1_coeff < 5-0 > A0_coeff < 5-0 > B3_coeff < 5-0 > B2_coeff < 5-0 > B1_coeff < 5-0 > B0_coeff < 5-0 > C3_coeff < 5-0 > C2_coeff < 5-0 > C1_coeff < 5-0 > C0_coeff < 5-0 > D3_coeff < 5-0 > D2_coeff < 5-0 > D1_coeff < 5-0 > D0_coeff < 5-0 > 23 DMA 2275, DMA 2286 8.4.5. CW Register Name cw_register lcw_even lcw_odd vcw_even vcw_odd dcw1_even dcw1_odd dcw2_even dcw2_odd dcw3_even dcw3_odd dcw4_even dcw4_odd Address 0600 0600 0640 0680 06c0 0700 0740 0780 07c0 0800 0840 0880 08c0 Function 96*8 bit 8*8 bit local control word 8*8 bit local control word 8*8 bit video control word 8*8 bit video control word 8*8 bit data control word 8*8 bit data control word 8*8 bit data control word 8*8 bit data control word 8*8 bit data control word 8*8 bit data control word 8*8 bit data control word 8*8 bit data control word CW Register bit address 0600H 0608H-0630H 0638H 0640H 0648H-0670H 0678H 0680H 0688H-06b0H 06b8H 06c0H 06c8H-06f0H 06f8H 0700H-0738H 0740H-0778H 0780H-07b8H 07c0H-07f8H 0800H-0838H 0840H-0878H 0880H-08b8H 08c0H-08f8H 7 6 5 4 3 2 1 0 LCW_even < 7-0 > LCW_even < 55-8 > LCW_even < 59-56 > LCW_odd < 7-0 > LCW_odd < 55-8 > LCW_odd < 59-56 > VCW_even < 7-0 > VCW_even < 55-8 > VCW_even < 59-56 > VCW_odd < 7-0 > VCW_odd < 55-8 > VCW_odd < 59-56 > DCW1_even < 59-0 > DCW1_odd < 59-0 > DCW2_even < 59-0 > DCW2_odd < 59-0 > DCW3_even < 59-0 > DCW3_odd < 59-0 > DCW4_even < 59-0 > DCW4_odd < 59-0 > 24 DMA 2275, DMA 2286 8.4.6. Error Buffer Name error_buffer buf1_error buf2_error buf3_error buf4_error buf5_error buf6_error buf7_error buf8_error Address 0c00 0c00 0c80 0d00 0d80 0e00 0e80 0f00 0f80 Function 8*16*8 bit 16*8 bit 16*8 bit 16*8 bit 16*8 bit 16*8 bit 16*8 bit 16*8 bit 16*8 bit bit 5-0: error_num bit 6: crc error bit 7: not defined (1 = error) Error Buffer bit address 0c00H 0c08H 0c10H 0c18H 0c20H 0c28H 0c30H 0c38H 0c40H 0c48H 0c50H 0c58H 0c60H 0c68H 0c70H 0c78H 0c80H-0cf8H 0d00H-0fffH 7 6 5 4 3 2 1 0 Pack1_error < 7-0 > Pack2_error < 7-0 > Pack3_error < 7-0 > Pack4_error < 7-0 > Pack5_error < 7-0 > Pack6_error < 7-0 > Pack7_error < 7-0 > Pack8_error < 7-0 > Pack9_error < 7-0 > Pack10_error < 7-0 > Pack11_error < 7-0 > Pack12_error < 7-0 > Pack13_error < 7-0 > Pack14_error < 7-0 > Pack15_error < 7-0 > Pack16_error < 7-0 > Buf2 Error Buf3-8 Error 25 DMA 2275, DMA 2286 8.4.7. Packet Buffer Name packet_buf packet_buf1 packet_buf2 packet_buf3 packet_buf4 packet_buf5 packet_buf6 packet_buf7 packet_buf8 Address 1000 1000 2800 4000 5800 7000 8800 a000 b800 Function 6144*8 bit 8*96*8 bit 8*96*8 bit 8*96*8 bit 8*96*8 bit 8*96*8 bit 8*96*8 bit 8*96*8 bit 8*96*8 bit 48 Byte Packet Buffer bit address 1000H 1008H 1010H 1018H 1020H 1028H 1030H 1038H 1040H-1178H 1180H 1188H 1190H 1198H 11a0H 11a8H 11b0H 11b8H 11c0H-12f8H 1300H-27f8H Packet Type Packet Data < 7-0 > Packet Data < 15-8 > Packet Data < 23-16 > Packet Data < 31-24 > Packet Data < 39-32 > Packet Data < 359-40 > Packet 3-16 Packet Type Packet Data < 7-0 > Packet Data < 15-8 > Packet Data < 23-16 > Packet Data < 31-24 > Packet Data < 39-32 > Packet Data < 359-40 > PA < 7-0 > CI PA < 9, 8 > 7 6 5 4 3 2 1 0 PA < 7-0 > CI PA < 9, 8 > 26 DMA 2275, DMA 2286 96 Byte Packet Buffer bit address 1000H 1008H 1010H 1018H 1020H 1028H 1030H 1038H 1040H-12e0H 12e8H 12f0H 12f8H 1300H 1308H 1310H 1318H 1320H 1328H 1330H 1338H 1340H-15e0H 15e8H 15f0H 15f8H 1600H-27f8H Packet 3-8 Packet Type Packet Data < 7-0 > Packet Data < 15-8 > Packet Data < 23-16 > Packet Data < 31 -24 > Packet Data < 39-32 > Packet Data < 719-40 > PA < 7-0 > CI PA < 9, 8 > Packet Type Packet Data < 7-0 > Packet Data < 15-8 > Packet Data < 23-16 > Packet Data < 31-24 > Packet Data < 39-32 > Packet Data < 719-40 > 7 6 5 4 3 2 1 0 PA < 7-0 > CI PA < 9, 8 > 27 DMA 2275, DMA 2286 8.4.8. Line 625 Buffer Name line_625_buf Address d000 Function 28*8 bit Line 625 Buffer bit address d000H d008H d010H d018H d020H d028H d030H d038H d040H d048H d050H d058H d060H d068H d070H d078H d080H d088H d090H d098H d0a0H d0a8H d0b0H d0b8H d0c0H d0c8H d0d0H d0d8H TDM _Err BCH < 7-0 > BCH < 13-8 > LINKS 7 6 5 4 3 2 1 0 UDT CHID < 7-0 > CHID < 15-8 > SDFSCR MVSCG CAFCNT < 7-0 > CAFCNT < 15-8 > CAFCNT < 19-16 > Unallocated BCH < 7-0 > SDF _Err BCH < 13-8 > FCNT UDF TDMCID TDMS < 7-0 > TDMS < 15-8 > TDMS < 23-16 > TDMS < 31-24 > TDMS < 39-32 > TDMS < 47-40 > TDMS < 55-48 > TDMS < 61-56 > 28 DMA 2275, DMA 2286 8.4.9. Scratch Buffer Name scratch_buf Address e000 Function 1024*8 bit 8.5. FP Memory Map Name frame_count line_count chroma_offset luma_offset pan_fifo Address 019 020 033 034 036 037 038 039 040 041 042 091 248 249 250 251 252 253 254 255 Function 12 bit 12 bit 12 bit 12 bit 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit bit 4-0: bit 5: bit 6: bit 7: bit 8: bit 11-9: fcnt flywheel line counter 2's complement 2's complement 2's complement 2's complement 2's complement 2's complement 2's complement 2's complement 2's complement packet counter (fifo output) (fifo input) packet_count buf1_status buf2_status buf3_status buf4_status buf5_status buf6_status buf7_status buf8_status buffer pointer buffer appl. buffer inc. buffer enable link status not used (0 = standard/1 = ring) (0 = 96 byte/1 = 48 byte) (0 = close/1 = open) (1 = active) 29 FP Memory DMA 2275, DMA 2286 address EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE 11 10 9 8 Buf1_status < 8-0 > Packet_count Luma_offset Line_count Frame_count Chroma_offset Pan_fifo 7 6 bit 5 4 3 2 1 0 30 36-42 251 250 249 248 255 254 253 252 34 33 20 19 91 Buf4_status < 8-0 > Buf3_status < 8-0 > Buf2_status < 8-0 > Buf8_status < 8-0 > Buf7_status < 8-0 > Buf6_status < 8-0 > Buf5_status < 8-0 > DMA 2275, DMA 2286 9. Specifications 9.1. Outline Dimensions Fig. 9-1: DMA 2275/2286 in 68-pin PLCC package Weight approx. 4.5 g, Dimensions in mm 9.2. Pin Connections Pin Nr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Name DMA 2275 Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Leave Vacant Signal Name DMA 2286 Sound RAM Data Sound RAM Address A0 Sound RAM Address A1 Sound RAM Address A2 Sound RAM Address A3 Sound RAM Address A4 Sound RAM Read/Write Sound RAM RAS Sound RAM Address A5 Sound RAM Address A6 Sound RAM Address A7 IM Bus Clock IM Bus Ident IM Bus Data Reset M Main Clock Burst Sync Leave Vacant I/O Input/Output Output Output Output Output Output Output Output Output Output Output Input Input Input/Output Input Input Input Symbol SDIO SA0 SA1 SA2 SA3 SA4 SR/W SRAS SA5 SA6 SA7 IMC IMI IMD RES MCLK BSYNC 31 DMA 2275, DMA 2286 Pin Connections, continued Pin Nr. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Signal Name DMA 2275 Burst Data VBI Data Corrected Packet Data Packet Data Descrambled Packet Data Baseband B0 Baseband B1 Baseband B2 Baseband B3 Baseband B4 Baseband B5 Baseband B6 Baseband B7 Ground Ground Ground Ground Ground Leave Vacant Supply Voltage, +5 V Baseband B7 Baseband B6 Baseband B5 Baseband B4 Baseband B3 Baseband B2 Baseband B1 Baseband B0 IM Bus Busy Ground Acq. RAM CAS Supply Input Input Input Input Input Input Input Input Output Test Input Output VSUP BI7 BI6 BI5 BI4 BI3 BI2 BI1 BI0 IMBUS GND ACAS Signal Name DMA 2286 I/O Input Output Output Input Output Output Output Output Output Output Output Output Output Supply Test Output Test Output Test Input Test Input Symbol BDAT VBIDAT CPDAT PDAT DPDAT BO0 BO1 BO2 BO3 BO4 BO5 BO6 BO7 GND GND GND GND GND 32 DMA 2275, DMA 2286 Pin Connections, continued Pin Nr. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Leave Vacant Leave Vacant Leave Vacant Leave Vacant Signal Name DMA 2275 Signal Name DMA 2286 Acq. RAM Data Acq. RAM Address A0 Acq. RAM Address A1 Acq. RAM Address A2 Acq. RAM Address A3 Acq. RAM Address A4 Acq. RAM Read/Write Acq. RAM RAS Acq. RAM Address A5 Acq. RAM Address A6 Acq. RAM Address A7 Ground Ground Supply Voltage, +5 V S_Bus Ident Audio Clock S_Bus Data Leave Vacant Sound RAM CAS Output SCAS I/O Output Output Output Output Output Output Output Output Output Output Output Supply Test Input Supply Input Input Output Symbol ADIO AA0 AA1 AA2 AA3 AA4 AR/W ARAS AA5 AA6 AA7 GND GND VSUP SBI ACLK SBD Note: Symbols for pin numbers 1 to 11, 64 to 66 and 68 are valid only for DMA 2286. 33 DMA 2275, DMA 2286 9.3. Pin Configuration Pin 8 - Sound RAM Row Address Select Output (Fig. 9-11) This pin supplies the Row Address Select signal (RAS) to the external sound RAM. SCAS SBD ACLK SBI VSUP GND GND SDIO SA0 SA1 SA2 SA3 SA4 SR/W SRAS SA5 Pins 12, 13 and 14 - IM Bus Connection (Figs. 9-3 and 9-7) These pins connect the DMA 2275/2286 to the IM bus. Via the IM bus the DMA 2275/2286 communicates with the CCU Central Control Unit. Pin 15 - Reset Input (Fig. 9-6) Pin 15 is used for hardware reset. Reset is actuated at Low level, and at High level the DAM 2275/2286 is ready for operation. Pin 16 - M Main Clock Input (Fig. 9-5) By means of this input, the DMA 2275/2286 receives the required main clock signal of 20.25 MHz form the MCU 2600 Clock Generator IC. Pin 17 - Burst Sync Input (Fig. 9-3) By means of this input, the DMA 2275/2286 receives the required burst sync pulse from the DMA 2271/2281. This sync pulse is used both as line sync and frame sync. Pin 19 - Burst Data Input (Fig. 9-3) By means of this input, the DMA 2275/2286 receives the decoded burst data of each line from the DMA 2271/2281. Pin 20 - VBI Data Output (Fig. 9-11) This pin supplies the descrambled burst data of each line. This signal may serve as an input signal for the TPU 2735 Teletext Processor. Pin 21 - Corrected Packet Data Output (Fig. 9-11) This pin supplies descrambled and error corrected packets from two subframes required by external teletext or other data processors. Pin 22 - Packet Data Input (Fig. 9-3) Via this pin, the DMA 2275/2286 receives packets of one subframe from pin 55 of the DMA 2271/2281. These packets are already de-interleaved, with golay-corrected header and error-corrected PT byte. Pin 23 - Descrambled Packet Data Output (Fig. 9-11) This pin supplies descrambled sound packets from one subframe to pin 56 of the DMA 2271/2281. Pins 24 to 31 - Baseband B0 to B7 Output (Fig. 9-11) Via these pins, the DMA 2275/2286 delivers the digital baseband signal including the descrambled video signal to the DMA 2271/2281, where it is decoded into luma, chroma and sound signals. Pins 32 to 26 and 48, 61 and 62 - Ground These pins must be connected to the negative (ground) of the supply voltage. SA6 SA7 IMC IMI IMD RES MCLK BSYNC BDAT VBIDAT CPDAT PDAT DPDAT BO0 BO1 BO2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 21 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 AA7 AA6 AA5 ARAS AR/W AA4 AA3 AA2 AA1 AA0 ADIO ACAS GND IMBUS BI0 BI1 BI2 DMA 2286 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 BO3 BO4 BO5 BO6 BO7 GND GND GND GND GND BI7 VSUP BI6 BI5 BI4 BI3 Fig. 9-2: DMA 2286 in 68-pin PLCC package 9.4. Pin Descriptions Pin 1 - Sound RAM Data Input/Output (Fig. 9-8) Pin 1 serves as output for writing sound data into the external sound RAM and as input for reading sound data from that RAM. Pins 2 to 6 and 9 to 11 - Sound RAM Address A0 to A7 Output (Fig. 9-11) These pins are used for addressing the external sound RAM. Pin 7 - Sound RAM Read/Write Output (Fig. 9-11) By means of this output the external sound RAM is switched to the read or write mode as required. 34 DMA 2275, DMA 2286 Pins 38 and 63 - Supply Voltage These pins must be connected to the positive supply voltage. Pins 39 to 46 - Baseband B7 to B0 Input (Fig. 9-4) Via these pins,the DMA 2275/2286 receives the digitized baseband signal coming either from the VCU 2133 Video Codec in a 7-bit parallel Gray code or from any other A/D converter in 8-bit parallel binary code. Pin 47 - IM Bus Busy Output (Fig. 9-11) This pin supplies a signal which indicates that the IM bus interface of the DMA 2275/2286 is busy. As long as this pin delivers a High level signal there should be no IM bus transfer to or from the DMA 2275/2286. Pin 49 - Acq. RAM Column Address Select Output (Fig. 9-10) This pin supplies the Column Address select signal (CAS) to the external acquisition RAM. Pin 50 - Acq. RAM Data Input/Output (Fig. 9-8) Pin 50 serves as output for writing data into the external acquisition RAM and as input for reading data from that RAM. Pins 51 to 55 and 58 to 60 - Acq. RAM Address A0 to A7 Output (Fig. 9-10) These pins are used for addressing the external acquisition RAM. Pin 56 - Acq. RAM Read/Write Output (Fig. 9-10) By means of this output the external acquisition RAM is switched to the read or write mode as required. Pin 57 - Acq. RAM Row Address Select Output (Fig. 9-10) This pin supplies the Row Address Select signal (RAS) to the external acquisition RAM. Pin 64 - S Bus Ident Input (Fig. 9-3) Via this input, the DMA 2286 receives the ident signal of the serial 3-line S bus from the DMA 2281. Pin 65 - Audio Clock Input (Fig. 9-5) By means of this input, the DMA 2286 receives the required audio clock signal of 18.432 MHz from the DMA 2281. Pin 66 - S Bus Data Output (Fig. 9-9) This pin supplies the digital sound signal to the AMU 2481 Audio Mixer and can be connected to the S Bus Data output of the DMA 2281. Only one S Bus Data output should be activated for one S Bus sound channel. Pin 68 - Sound RAM Column Address Select Output (Fig. 9-11) This pin supplies the Column Address Select signal (CAS) to the external sound RAM. P N P N GND Fig. 9-5: Input Pins16 and 65 9.5. Pin Circuits The following figures schematically show the circuitry at the various pins. The integrated protection structures are not shown. The letter "P" means P-channel, the letter "N" N-channel. VSUP P N GND Fig. 9-3: Input Pins 12, 13, 17, 19, 22 and 64 VSUP P N P N BIAS Fig. 9-4: Input Pins 39 to 46 GND VSUP VSUP P P N N P GND Fig. 9-6: Input Pin 15 N VSUP P N N GND Fig. 9-7: Input/Output Pin 14 35 DMA 2275, DMA 2286 VSUP P P VSUP P N N GND Fig. 9-8: Input/Output Pins 1 and 50 N GND Fig. 9-10: Output Pins 49, 51 to 60 VSUP VSUP P N GND Fig. 9-9: Output Pin 66 GND N Fig. 9-11: Output Pins 2 to 11, 20, 21, 23 to 31, 47 and 68 9.6. Electrical Characteristics All voltages are referred to ground. 9.6.1. Absolute Maximum Ratings Symbol TA TS VSUP VI VO IO Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input Voltage, all Inputs Output Voltage, all Outputs Output Current, all Outputs Pin No. - - 38, 63 - - - Min. 0 -40 - -0.3 V -0.3 V -10 Max. 65 +125 6 VSUP VSUP +10 Unit C C V - - mA 36 DMA 2275, DMA 2286 9.6.2. Recommended Operating Conditions Symbol TA VSUP VIMIL VIMIH Rext fI tIM1 tIM2 tIM3 tIM4 tIM5 tIM6 tIM7 tIM8 tIM9 tIM10 VREIL VREIH tREIL VMIDC VMIAC tMIH tMIL tMIHL fM Parameter Ambient Operating Temperature Supply Voltage IM Bus Input Low Voltage IM Bus Input High Voltage External Pull-Up Resistor I IM Bus Clock Frequency I Clock Input Delay Time after IM Bus Ident Input I Clock Input Low Pulse Time I Clock Input High Pulse Time I Clock Input Setup Time before Ident Input High I Clock Input Hold Time after Ident Input High I Clock Input Setup Time before Ident End-Pulse Input IM Bus Data Input Delay Time after I Clock Input IM Bus Data Input Setup Time before I Clock Input IM Bus Data Input Hold Time after I Clock Input IM Bus Ident End-Pulse Low Time Reset Input Low Voltage Reset Input High Voltage Reset Input Low Time M Clock Input D.C. Voltage M Clock Input A.C. Voltage (p-p) M Clock Input High/Low Ratio M Clock Input High/Low Transition Time M Clock Input Frequency 16 15 Pin No. - 38, 63 12 to 14 Min. 0 4.75 - 2.0 1.0 0.05 0 500 500 0 250 1.0 0 0 0 1.0 - 2.0 2 1.5 0.8 0.9 - - Typ. - 5.0 - - - - - - - - - - - - - - - - - - - 1.0 - 20.25 Max. 65 5.25 0.8 - - 1000 - - - - - - - - - - 0.8 - - 3.5 2.5 1.1 0.15 fM - Unit C V V V k kHz ns ns ns ns ns s ns ns ns s V V s V V - s MHz 37 DMA 2275, DMA 2286 Recommended Operating Conditions, continued Symbol VBBIL VBBIH VPDIL VPDIH VBIL VBIH tBIS tBIH VSIIL VSIIH tSIIL VAIDC VAIAC tAH tAL tA fA Parameter Burst Bus Input Low Voltage Burst Bus Input High Voltage Packet Data Input Low Voltage Packet Data Input High Voltage Baseband Input Low Voltage Baseband Input High Voltage Baseband Input Setup Time before falling edge of MCLK Baseband Input Hold Time after falling edge of MCLK S Bus Ident Input Low Voltage S Bus Ident Input High Voltage S Bus Ident Input Low Time A Clock Input D.C. Voltage A Clock Input A.C. Voltage (p-p) A Clock Input High/Low Ratio A Clock Input High/Low Transition Time A Clock Input Frequency 65 64 39 to 46, 16 39 to 46 22 Pin No. 17, 19 Min. - 2.0 - 2.0 - 2.8 15 0 - 2.0 150 1.5 0.8 0.9 - - Typ. - - - - - - - - - - - - - 1.0 - 18.432 Max. 0.8 - 0.8 - 2.2 - 50 - 0.4 - - 3.5 2.5 1.1 0.15 fA - Unit V V V V V V ns ns V V ns V V - s MHz 38 DMA 2275, DMA 2286 9.6.3. Characteristics at TA = 0 to 65 C, VSUP = 4.75 to 5.25 V, fM = 20.25 MHz Symbol ISUP VIMDOL IIMDOH tIM8 tIM9 VVDOL VVDOH tVDOT tVDOD VPDOL VPDOH tPDOT tPDOD VBOL VBOH tBOT tBOD VIBOL VIBOH tIBOT VSDOL ISDOH tSDOD Parameter Supply Current IM Bus Data Output Low Voltage IM Bus Data Output High Current IM Bus Data Output Setup Time before IM Bus Clock Input IM Bus Data Output Hold Time after IM Bus Clock Input VBI Data Output Low Voltage VBI Data Output High Voltage VBI Data Output Transition Time VBI Data Output Delay Time after falling edge of MCLK Packet Data Output Low Voltage Packet Data Output High Voltage Packet Data Output Transition Time Packet Data Output Delay Time after rising edge of MCLK Baseband Output Low Voltage Baseband Output High Voltage Baseband Output Transition Time Baseband Output Delay Time after falling edge of MCLK IM Bus Busy Output Low Voltage IM Bus Busy Output High Voltage IM Bus Busy Output Transition Time S Bus Data Output Low Voltage S Bus Data Output High Current S Bus Data Output Delay Time after falling edge of ACLK 66, 65 66 24 to 31, 16 47 21, 23, 16 24 to 31 20, 16 20 14, 12 Pin No. 38, 63 14 Min. - - Typ. 120 - Max. 160 0.4 Unit mA V IIMO = 5 mA VIMO = 5 V Test Conditions - - 10 A ns 0 - 500 0 - - ns - 2.4 - - - - - 0 0.4 - 10 - V V ns ns IL = 1.6 mA -IL = 0.1 mA CL = 10 pF 21, 23 - 2.4 - - - - 0.4 - 10 V V ns IL = 1.6 mA -IL = 0.1 mA CL = 10 pF - 0 - ns - 2.4 - - - - 0.4 - 10 V V ns IL= 1.6 mA IL = -0.1 mA CL = 10 pF - 20 - ns - 2.4 - - 0.4 - V V IL = 1.6 mA -IL = 0.1 mA CL = 10 pF ISO = 8 mA VSO = 5 V - - 10 ns - - - - - 20 0.3 10 - V A ns 39 DMA 2275, DMA 2286 9.6.4. Sound DRAM Interface Characteristics at TA = 0 to 65 C, VSUP = 4.75 to 5.25 V, fA = 18.432 MHz Symbol VDIL VDIH VDOL VDOH tDT tDIS tDIH tDHR tDS tDH VAOL VAOH tAT tRAH tASR tAR tCAH tASC VRASOL VRASOH tRAST tRAS tRP Parameter RAM Data Input Low Voltage RAM Data Input High Voltage RAM Data Output Low Voltage RAM Data Output High Voltage RAM Data Output Transition Time RAM Data Input Setup Time before CAS Output High RAM Data Input Hold Time after CAS Output High RAM Data Output Hold Time after RAS Output Low RAM Data Output Setup Time before CAS Output Low RAM Data Output Hold Time after CAS Output Low RAM Address Output Low Voltage RAM Address Output High Voltage RAM Address Output Transition Time Row Address Output Hold Time after RAS Output Low Row Address Output Setup Time before RAS Output Low Column Address Output Hold Time after RAS Output Low Column Address Output Hold Time after CAS Output Low Column Address Output Setup Time before CAS Output Low RAS Output Low Voltage RAS Output High Voltage RAS Output Transition Time RAS Output Low Pulsewidth RAS Output Precharge Time 8 2 to 6, 9 to 11, 8, 8 68 2 to 6, 9 to 11 1, 8, 68 Pin No. 1 Min. - 2.0 - 2.4 3 Typ. - - - - - Max. 0.8 - 0.4 - 10 Unit V V V V ns IDO = 1.6 mA -IDO = 0.1 mA CL = 10 pF Test Conditions 0 - 75 ns 0 - 33 ns 140 - - ns 20 - - ns 80 - - ns - - 0.4 V IAO = 1.6 mA -IAO = 0.1 mA CL = 10 pF 2.4 - - V 3 - 10 ns 22 - - ns 30 - - ns 125 - - ns 70 - - ns 10 - - ns - 2.4 3 125 130 - - - - - 0.4 - 10 3000 - V V ns ns ns IRASO = 1.6 mA -IRASO = 0.1 mA CL = 10 pF 40 DMA 2275, DMA 2286 Sound DRAM Interface Characteristics, continued Symbol VCASOL VCASOH tCAST tCP tCAS tPC tRSH tRCD tCSH tCRP VWOL VWOH tWT tCWL tWCH tRCH tRRH Parameter CAS Output Low Voltage CAS Output High Voltage CAS Output Transition Time CAS Output Precharge Time CAS Output Low Pulsewidth Page Mode Cycle Time RAS Output Hold Time after CAS Output Low CAS Output Delay Time after RAS Output CAS Output Hold Time after RAS Output Low CAS Output Precharge Time before RAS Output Low WRITE Output Low Voltage WRITE Output High Voltage WRITE Output Transition Time WRITE Output Low before CAS Output High WRITE Output Hold Time after CAS Output Low WRITE Output Hold Time after CAS Output High WRITE Output Hold Time after RAS Output High 7, 8, 68 7 8, 68 Pin No. 68 Min. - 2.4 3 70 95 170 110 Typ. - - - - - - - Max. 0.4 - 10 - 150 - - Unit V V ns ns ns ns ns Test Conditions ICASO = 1.6 mA -ICASO = 0.1 mA CL = 10 pF 45 - - ns 170 - - ns 150 - - ns - 2.4 3 180 - - - - 0.4 - 10 - V V ns ns IWO = 1.6 mA -IWO = 0.1 mA CL = 10 pF 80 - - ns 50 - - ns 20 - - ns 41 DMA 2275, DMA 2286 9.6.5. Acquisition DRAM Interface Characteristics at TA = 0 to 65 C, VSUP = 4.75 to 5.25 V, fM = 20.25 MHz Symbol VDIL VDIH VDOL VDOH tDT tDIS tDIH tDHR tDS tDH VAOL VAOH tAT tRAH tASR tAR tCAH tASC VRASOL VRASOH tRAST tRAS tRP Parameter RAM Data Input Low Voltage RAM Data Input High Voltage RAM Data Output Low Voltage RAM Data Output High Voltage RAM Data Output Transition Time RAM Data Input Setup Time before CAS Output High RAM Data Input Hold Time after CAS Output High RAM Data Output Hold Time after RAS Output Low RAM Data Output Setup Time before CAS Output Low RAM Data Output Hold Time after CAS Output Low RAM Address Output Low Voltage RAM Address Output High Voltage RAM Address Output Transition Time Row Address Output Hold Time after RAS Output Low Row Address Output Setup Time before RAS Output Low Column Address Output Hold Time after RAS Output Low Column Address Output Hold Time after CAS Output Low Column Address Output Setup Time before CAS Output Low RAS Output Low Voltage RAS Output High Voltage RAS Output Transition Time RAS Output Low Pulsewidth RAS Output Precharge Time 57 51 to 55, 58 to 60, 49, 49 57 51 to 55, 58 to 60 50, 49, 57 Pin No. 50 Min. - 2.0 - 2.4 3 Typ. - - - - - Max. 0.8 - 0.4 - 10 Unit V V V V ns IDO = 1.6 mA -IDO = 0.1 mA CL = 10 pF Test Conditions - - 50 ns 25 - 45 ns 250 - - ns 40 - - ns 130 - - ns - - 0.4 V IAO = 1.6 mA -IAO = 0.1 mA CL = 10 pF 2.4 - - V 3 - 10 ns 60 - - ns 100 - - ns 80 - - ns 50 - - ns 20 - - ns - 2.4 3 - 100 - - - 1600 - 0.4 - 10 - - V V ns ns ns IRASO = 1.6 mA -IRASO = 0.1 mA CL = 10 pF 42 DMA 2275, DMA 2286 Acquisition DRAM Interface Characteristics, continued Symbol VCASOL VCASOH tCAST tCP tCAS tPC tRSH tRCD tCSH tCRP VWOL VWOH tWT tCWL tWCH tRCH tRRH Parameter CAS Output Low Voltage CAS Output High Voltage CAS Output Transition Time CAS Output Precharge Time CAS Output Low Pulsewidth Page Mode Cycle Time RAS Output Hold Time after CAS Output Low CAS Output Delay Time after RAS Output CAS Output Hold Time after RAS Output Low CAS Output Precharge Time before RAS Output Low WRITE Output Low Voltage WRITE Output High Voltage WRITE Output Transition Time WRITE Output Low before CAS Output High WRITE Output Hold Time after CAS Output Low WRITE Output Hold Time after CAS Output High WRITE Output Hold Time after RAS Output High 56, 49, 57 56 49, 57 Pin No. 49 Min. - 2.4 3 80 90 200 75 Typ. - - - - - - - Max. 0.4 - 10 - 110 - - Unit V V ns ns ns ns ns Test Conditions ICASO = 1.6 mA -ICASO = 0.1 mA CL = 10 pF 75 - - ns 170 - - ns 200 - - ns - 2.4 3 275 - - - - 0.4 - 10 - V V ns ns IWO = 1.6 mA -IWO = 0.1 mA CL = 10 pF 125 - - ns 20 - - ns 25 - - ns 43 DMA 2275, DMA 2286 9.6.6. Waveforms H Ident L H Clock L H Data L LSB Address MSB LSB Data MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 16 or 24 A Section A H Ident L tIM1 tIM2 H Clock L tIM7 H Data L tIM8 tIM9 tIM3 B Section B C Section C tIM10 tIM4 tIM5 tIM6 Address LSB Address MSB Data MSB Fig. 9-12: IM bus waveforms H S-Ident L H S-Clock L H S-Data L 16 Bit Sound 1 16 Bit Sound 2 16 Bit Sound 3 16 Bit Sound 4 64 Clock Cycles A Section A H S-Ident L tS1 H S-Clock L tS4 H S-Data L tS5 tS2 tS3 B Section B tS6 LSB of Sound 1 MSB of Sound 4 Fig. 9-13: S bus waveforms 44 DMA 2275, DMA 2286 tCWL WE VOH VOL VOH VOL tRCD tAR tRAS tRRH tWCH tRSH tCP tCAS RAS tCSH tPC tRP CAS VOH VOL tASR tRAH tASC tCAH COLUMN ADDRESS 1 COLUMN ADDRESS 14 tRCH tCRP ROW ADDR. DRAM VOH ADDR. VOL VOH VOL VOH VOL ROW ADDR. COLUMN ADDR. 0 tDS tDH VALID DATA tDHR DOUT VALID DATA VALID DATA DIN VALID tDIS DATA tDIH VALID DATA VALID DATA Fig. 9-14: DRAM waveform 45 DMA 2275, DMA 2286 10. References 1. Specification of the systems of the MAC/packet family. EBU Technical Document 3258-E, Oct. 1986. 2. Data Sheet DMA 2271, DMA 2281 C/D/D2-MAC Decoder ITT Semiconductors 46 DMA 2275, DMA 2286 47 DMA 2275, DMA 2286 MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany by Simon Druck GmbH & Co., Freiburg (5/92) Order No. 6251-330-1E All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. 48 MICRONAS INTERMETALL |
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